Industry expertise in LabVIEW FPGA programming across the full range of NI FPGA hardware including Compact RIO (cRIO) and Virtex-5 LX110 FPGA.
Field-programmable gate arrays (FPGAs)
For some R&D, test and prototype applications, FPGAs can offer great advantages in terms of performance, time to market, cost, reliability and long-term maintenance.
We are able to support you with expertise in FPGA programming across National Instrument’s full range including Compact RIO (cRIO) and Virtex-5 LX110 FPGA.
Our experience covers:
- The range of Xilinx based FPGAs (Virtex II through to Virtex 5)
- Direct interaction with primitives and macros for the underlying architecture
- Implementing 200MHz DDR comms to 16-bit parallel ADC (which also involved implementing instance of digital clock manager – DCM – to adjust clock skew on pin by pin basis)
- Using Xilinx Coregen tools to implement and incorporate pre-generated blocks such as FIR filters and dual port memory etc
- Development of standard protocols (eg SPI and I2C) to external devices (eg Memory, ADCs and DACs)
- Using Xilinx floor-planner tools to develop Location based constraints files
- Linking VHDL with other 3rd party tools, including Xilinx Schematics (block diagram) and LabVIEW FPGA (CLIP nodes)
- Altera FPGAs as the underlying architecture and VHDL structure are the same.
Austin Consultants have been a great pleasure to work with, extremely supporting to our requirements and needs and offering support and advice with regards to NI hardware and software requirements. The level of final solution was over and above our original expectation and has provided us with a high precision industry leading Creep Lab Remote monitoring platform that can be viewed from anywhere in the world.
Case Study: Imperial College London
We recently worked with the Department of Mechanical Engineering at Imperial College, London, developing a networked Creep Logging System used as a long-term (multiple year) robust data logger. The system setup included a central PC connected via a network to a set of five cRIOs. Each cRIO had its own LVFT configuration (4-20mA sensors), where a single test can choose a number of channels from a selection of cRIOs.
The system had a fail-safe mode so that if any RIO drops out, the configuration is always stored on the remaining RIOs and when the failing RIO re-boots, it is automatically repopulated.
The system also contains multiple user access levels and can ftp in real-time and load post processed date depending on the viewing mode. With the PC being networked based it has allowed the whole system to run over the internet on a VPN so that all the tests can be run and checked on remotely.
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