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If you have designed an FPGA code that you want to test with real-life timing but without allowing to cooperate with real-life signals, you can use simulated signals and DMA FIFOs. Our LabVIEW Tip: Testing FPGA logic without real life signals using uplink/downlink DMA channels – demonstrates how to build up an array that is representative to your real-life input signal and send it down to your already compiled FPGA code via a DMA FIFO:

You can read the outputs of your logic using another DMA FIFO. You can also play with timing, if you include the Loop Timer express VI.

LabVIEW Tip: Testing FPGA Logic without real life signals demo screen

You can read the outputs of your logic using another DMA FIFO. You can also play with timing, if you include the Loop Timer express VI.